1. Field of the Invention
The invention relates to a memory cell having a vertical selection transistor, an arrangement of these memory cells, and a method for producing these memory cells.
2. Description of the Related Art
Information can be stored and read out again with the aid of rewritable semiconductor memories. In the case of a DRAM semiconductor memory, the information is stored in the form of a specific charge in a storage capacitor. Each DRAM memory cell in this case comprises a trench capacitor and a selection transistor. A charge that represents the information to be stored is stored in the trench capacitor. The selection transistor, by contrast, serves as a switch for the readin and/or readout operation. When the selection transistor of the memory cell is activated by means of the associated word line, the stored charge is transmitted to a bit line of the semiconductor memory. The voltage on the bit line can be evaluated via an evaluation circuit such that the charge stored in the trench capacitor can be detected as information.
The performance of such memory cells is fundamentally determined in this case both by the properties of the individual components themselves and by their interplay.
The continuous trend to ever more powerful memories increasingly necessitates higher integration densities of the semiconductor structures. In order in this case to reduce the areal requirement of DRAM memory cells, concepts associated with a vertically arranged selection transistor are increasingly being investigated.
DE 199 54 867 C1 discloses a DRAM cell arrangement and a method for producing it in the case of which a vertical selection transistor is provided. The known cell arrangement has a trench capacitor that is connected in the upper end region to a horizontally arranged source-drain region. Constructed in a fashion offset from the upper source-drain region is a lower source-drain region that is connected to a vertical connecting channel. The connecting channel is led upward from the lower source-drain region to the bit line. A gate region that constitutes a part of a word line is constructed parallel to the connecting channel. The known cell arrangement has the disadvantage that a relatively large area is required for constructing the memory cell.
U.S. Pat. No. 6,363,484 discloses a generic memory cell, a corresponding arrangement of memory cells and a method for producing such a memory cell. In the case of this known memory cell, a cylindrically shaped vertical selection transistor is constructed in the upper region of a trench hole. U.S. Pat. No. 6,406,970 B1 further discloses configuring trench holes both in trench-shaped and angular fashions.